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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D-Type Latch with 3-State Output
The MC74VHC373 is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * * * * * * * * * * * High Speed: tPD = 5.0ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.9V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 186 FETs or 46.5 Equivalent Gates
MC74VHC373
DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-04
DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02
M SUFFIX 20-LEAD SOIC EIAJ PACKAGE CASE 967-01 ORDERING INFORMATION MC74VHCXXXDW SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
PIN ASSIGNMENT
OE Q0 D0 D1 Q1 Q2 D2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
LE OE
11 1
D3 Q3 GND
FUNCTION TABLE
INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L No Change Z
6/97
(c) Motorola, Inc. 1997
1
REV 1
II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII III I III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
II I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I III I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MC74VHC373
MAXIMUM RATINGS*
Symbol VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage Parameter SOIC Packages TSSOP Package - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0 - 0.5 to + 7.0 Value - 20 75 25 20 500 450 Unit mW mA mA mA mA
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
MOTOROLA Symbol S bl Symbol VOH VCC VOL Vout VIH tr, tf VIL Vin TA Iin
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter P
Parameter
Vin = 5.5 V or GND
Vin = VIH or VIL IOL = 4mA IOL = 8mA
Vin = VIH or VIL IOL = 50A
Vin = VIH or VIL IOH = - 4mA IOH = - mA8
Vin = VIH or VIL IOH = - 50A
Test C di i T Conditions
VCC = 3.3V VCC = 5.0V
0 to 5.5
2.0 3.0 to 5.5
2.0 3.0 to 5.5
VCC V
3.0 4.5
2.0 3.0 4.5
3.0 4.5
2.0 3.0 4.5
2
- 40
Min
2.0
0 0
0
0
1.50 VCC x 0.7
2.58 3.94
Min
1.9 2.9 4.4
VCC
+ 85
Max
100 20
5.5
5.5
TA = 25C
ns/V
Unit
_C
_C
Typ
V
V
V
V
V
V
0.0 0.0 0.0
2.0 3.0 4.5
0.50 VCC x 0.3
0.1
0.36 0.36
Max
0.1 0.1 0.1
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1 1.50 VCC x 0.7 TA = - 40 to 85C 2.48 3.80 Min 1.9 2.9 4.4
v
0.50 VCC x 0.3
1.0 0.44 0.44 Max 0.1 0.1 0.1
v
Unit Ui
A V V V V
II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Symbol S bl Symbol tOSLH, tOSHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Cout ICC IOZ Cin Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Output to Output Skew Output Disable Time, OE to Q Output Enable Time, OE to Q Maximum Propagation Delay, LE to Q Maximum Propagation Delay, D to Q Maximum Quiescent Supply Current Maximum Three-State Leakage Current Parameter Parameter P Vin = VCC or GND Vin = VIL or VIH Vout = VCC or GND Test Conditions VCC = 5.5 0.5V (Note 1.) VCC = 3.3 0.3V (Note 1.) VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V Test C di i T Conditions VCC V 5.5 5.5 CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF Min Min TA = 25C Typ TA = 25C Typ 6.5 9.5 5.5 7.0 7.3 9.8 5.0 6.5 7.3 9.8 4.9 6.4 7.0 9.5 6 4 Typical @ 25C, VCC = 5.0V 0.25 Max 4.0 13.2 Max 11.4 14.9 11.4 14.9 11.0 14.5 8.1 10.1 1.0 1.5 9.2 7.2 9.2 7.2 9.2 10 TA = - 40 to 85C Min TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
CPD Power Dissipation C P Di i i Capacitance (N i (Note 2 ) 2.) 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1 Symbol S bl VOLP VOLV VIHD VILD Maximum Low Level Dynamic Input Voltage Minimum High Level Dynamic Input Voltage Quiet Output Minimum Dynamic VOL Quiet Output Maximum Dynamic VOL Parameter P
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
3 - 0.6 Typ 0.6 27 TA = 25C - 0.9 Max 1.5 3.5 0.9
MC74VHC373
2.5
40.0
Max
10.5
15.0
13.5 17.0
13.5 17.0
13.0 16.5
Max
8.5 10.5
8.5 10.5
9.5 11.5
1.0
1.5
10
MOTOROLA Unit Ui pF F Unit Ui Unit V V V V A A pF pF ns ns ns ns ns ns
MC74VHC373
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25C Symbol S bl tw(h) tsu th Parameter P Minimum Pulse Width, LE Minimum Setup Time, D to LE Minimum Hold Time, D to LE Test C di i Conditions T VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V Typ Limit 5.0 5.0 4.0 4.0 1.0 1.0 TA = - 40 to 85C Limit 5.0 5.0 4.0 4.0 1.0 1.0 Unit Ui ns ns ns
SWITCHING WAVEFORMS
VCC D tPLH Q 50% VCC Q 50% VCC 50% GND tPHL tPLH tPHL tw LE 50% GND
VCC
Figure 1.
OE VCC 50% GND tPZL Q 50% VCC tPZH Q 50% VCC tPHZ VOL -0.3V HIGH IMPEDANCE tPLZ HIGH IMPEDANCE VOL +0.3V LE D
Figure 2.
VALID 50% tsu th VCC 50% GND VCC GND
Figure 3.
Figure 4.
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC373
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT CL* 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0 3 D Q D1 4 D Q D2 7 D Q D3 8 D Q D4 13 D Q D5 14 D Q D6 17 D Q D7 18 D Q
LE 11
LE
LE
LE
LE
LE
LE
LE
LE
OE
1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
INPUT EQUIVALENT CIRCUIT
INPUT
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
MOTOROLA
MC74VHC373
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
MOTOROLA
6
IIII IIII IIII
SECTION N-N M DETAIL E
20
11
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC373
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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VHC Data - Advanced CMOS Logic DL203 -- Rev 1
7
MC74VHC373/D MOTOROLA

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